Modern computers systems include classes of processors (e.g. Itanium™ based platforms) that may be able to correct and recover from certain kinds of processor and platform errors without crashing. Such platforms are referred to as platforms capable of handling corrected platform errors (CPEs). However, even though these systems are resilient to certain types of errors and continue operation despite the occurrence of the errors, there needs to be some accounting of the CPEs for use and analysis by the operating system or other manageability software.
One method of gathering CPE data is based on an interrupt polling model. In an interrupt model based system, the operating system is sent an interrupt upon the occurrence of an error. If the platform supports the interrupt model, the system firmware will need to communicate with the operating system through corrected platform error interrupt (CPEI) structures as defined in the Platform Interrupt Sources Structure of Advanced Configuration and Power Interface (ACPI) specification and the platform system abstraction layer specification. However, in some instances such as mission-critical server systems, the interrupt model for the corrected platform errors is not a preferred solution due to the potential of interrupt storms, in the case of the occurrence of a large number of simultaneous platform errors.
Therefore, an alternative mechanism for collecting corrected platform errors is needed to avoid potential problems such as interrupt storm. Additionally, a mechanism for storing and updating the CPE data is needed in conjunction with the new method of collecting CPE data for updating processor polling information changes due to dynamic reconfigurations of systems during runtime.